Publications

Conference Proceedings

  • S. Park*, K. Shin*, D. Lee, M. Kang, S. Lee, Y. Park, M. Seok, and D. Jeon, “A 5.6μW 10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy,” IEEE Symposium on VLSI Circuits (VLSIC), accepted. (*Equal Contribution)
  • S. Woo, S. Lee, and D. Jeon, “ALAM: Averaged Low-Precision Activation for Memory-Efficient Training of Transformer Models,” International Conference on Learning Representations (ICLR), accepted.
  • M. Kang, S. Kim, Y. Park, S. Jeong, and D. Jeon, “A 28nm All-Digital Droop Detection and Mitigation Circuit Using A Shared Dual-Mode Delay Line with 14.8% Vmin Reduction and 42.9% Throughput Gain,” IEEE Custom Integrated Circuits Conference (CICC), accepted.
  • S. Jeong, J. Oh, and D. Jeon, “A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference,” IEEE Custom Integrated Circuits Conference (CICC), accepted.
  • S. Lee, J. Park, and D. Jeon, “A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array,” IEEE European Solid-State Circuits Conference (ESSCIRC), 2023.
  • S. Woo and D. Jeon, “Learning with Auxiliary Activation for Memory-Efficient Training,” International Conference on Learning Representations (ICLR), 2023.
  • S. Park, S. Lee, J. Park, H.-S. Choi, and D. Jeon, “A 0.81mm2 740µW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), 2023.
  • S. Jeong, J. Park, and D. Jeon, “A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training,” IEEE European Solid-State Circuits Conference (ESSCIRC), 2022.
  • S. Lee, J. Park, and D. Jeon, “Toward Efficient Low-Precision Training: Data Format Optimization and Hysteresis Quantization,” International Conference on Learning Representations (ICLR), 2022.
  • S. Woo, J. Park, J. Hong, and D. Jeon, “Activation Sharing with Asymmetric Paths Solves Weight Transport Problem without Bidirectional Connection,” Conference on Neural Information Processing Systems (NeurIPS), 2021.
  • J. Park*, S. Lee*, and D. Jeon, “A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree,” IEEE International Solid-State Circuits Conference (ISSCC), 2021. (*Equal Contribution)
  • S. Park and D. Jeon, “A Modified Serial Commutator Architecture for Real-Valued Fast Fourier Transform,” IEEE International Workshop on Signal Processing Systems (SiPS), 2020.
  • J. Park, J. Lee, and D. Jeon, “A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback,” IEEE International Solid-State Circuits Conference (ISSCC), 2019.
  • T. Jang, S. Jeong, D. Jeon, K. D. Choo, D. Sylvester, and D. Blaauw, “A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment,” IEEE International Solid-State Circuits Conference (ISSCC), 2017.
  • S. M. A. Zeinolabedin, A. T. Do, D. Jeon, D. Sylvester, and T. T.-H. Kim, “A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS,” IEEE Symposium on VLSI Circuits (VLSIC), 2016.
  • D. Jeon, N. Ickes, P. Raina, H.-C. Wang, and A. P. Chandrakasan, “A 0.6V, 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired,” IEEE International Solid-State Circuits Conference (ISSCC), 2016.
  • D. Jeon, Q. Dong, Y. Kim, X. Wang, S. Chen, H. Yu, D. Blaauw, and D. Sylvester, “A 23mW Face Recognition Accelerator in 40nm CMOS with Mostly-Read 5T Memory,” IEEE Symposium on VLSI Circuits (VLSIC), 2015.
  • S. Jeong, W. Jung, D. Jeon, O. Berenfeld, H. Oral, G. Kruger, D. Blaauw, and D. Sylvester, “A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications,” IEEE Symposium on VLSI Circuits (VLSIC), 2015.
  • I. Lee, Y. Kim, S. Bang, G. Kim, H. Ha, Y.-P. Chen, D. Jeon, S. Jeong, W. Jung, M. H. Ghaed, Z. Foo, Y. Lee, J.-Y. Sim, D. Sylvester, and D. Blaauw, “Circuit techniques for miniaturized biomedical sensors,” IEEE Custom Integrated Circuits Conference (CICC), 2014.
  • D. Jeon, Y.-P. Chen, Y. Lee, Y. Kim, Z. Foo, G. Kruger, H. Oral, O. Berenfeld, Z. Zhang, D. Blaauw, and D. Sylvester, “An Implantable 64nW ECG Monitoring Mixed-Signal SoC for Arrhythmia Diagnosis,” IEEE International Solid-State Circuits Conference (ISSCC), 2014.
  • D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw and D. Sylvester, “A low-power VGA full-frame feature extraction processor ,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2013.
  • D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw and D. Sylvester, “A 470mV 2.7mW Feature Extraction-Accelerator for Micro-Autonomous Vehicle Navigation in 28nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), 2013.
  • M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester, “Extending Energy-Saving Voltage Scaling in Ultra Low Voltage Integrated Circuit Designs,” International Conference on IC Design and Technology (ICICDT), 2012, invited.
  • M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester, “Pipeline Strategy for Improving Optimal Energy Efficiency in Ultra-Low Voltage Design,” ACM/IEEE Design Automation Conference (DAC), 2011.
  • D. Jeon, M. Seok, C. Chakrabarti, D. Blaauw and D. Sylvester, “Energy-optimized high performance FFT processor,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2011.
  • M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester, “A 0.27V, 30MHz, 17.7nJ/transform 1024-pt complex FFT core with ultrapipelining,” IEEE International Solid-State Circuits Conference (ISSCC), 2011.

Journal Publications

  • W. Lee, K. Kim, W. Ahn, J. Kim, and D. Jeon, “A Real-Time Object Detection Processor with XNOR-based Variable-Precision Computing Unit,” IEEE Transactions on VLSI Systems (TVLSI), 2023.
  • Y. Ko, S. Kim, K. Shin, Y. Park, S. Kim, and D. Jeon, “A 65nm 12.92nJ/inference Mixed-Signal Neuromorphic Processor for Image Classification,” IEEE Transactions on Circuits and Systems II (TCAS-II), 2023.
  • Y. Park and D. Jeon, “A 270mA Self-Calibrating-Clocked Output-Capacitor-Free LDO with 0.15-1.15V Output Range and 0.183fs FoM,” IEEE Transactions on VLSI Systems (TVLSI), 2022.
  • J. Hong, S. Kim, and D. Jeon, “An Automatic Circuit Design Framework for Level Shifter Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022.
  • S. Kim, W. Lee, S. Kim, S. Park, and D. Jeon, “An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network,” IEEE Transactions on Circuits and Systems II (TCAS-II), 2022.
  • J. Park, S. Lee, and D. Jeon, “A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees,” IEEE Journal of Solid-State Circuits (JSSC), 2022.
  • C. Seong, W. Lee, and D. Jeon, “A Multi-Channel Spike Sorting Processor with Accurate Clustering Algorithm Using Convolutional Autoencoder,” IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), 2021.
  • G. Lee, S. Lee, and D. Jeon, “Dynamic Block-Wise Local Learning Algorithm for Efficient Neural Network Training,” IEEE Transactions on VLSI Systems (TVLSI), 2021.
  • K. Shin, D.-W. Jee, and D. Jeon, “A 65nm 0.6-1.2V Low-Dropout Regulator Using Voltage-Difference-to-Time Converter with Direct Output Feedback,” IEEE Transactions on Circuits and Systems II (TCAS-II), 2021.
  • J. Park, J. Lee, and D. Jeon, “A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback,” IEEE Journal of Solid-State Circuits (JSSC), 2020, invited.
  • S. Kim, J. Lee, I. Kwon, and D. Jeon, “TID-Tolerant Inverter Designs for Radiation-Hardened Digital Systems,” Nuclear Instruments and Methods in Physics Research Section A (NIMA), 2020.
  • S. Moon, K. Shin, and D. Jeon, “Enhancing Reliability of Analog Neural Network Processors,” IEEE Transactions on VLSI Systems (TVLSI), 2019.
  • J. Park, Y. Kwon, Y. Park, and D. Jeon, “Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors,” IEEE Access, 2019.
  • J. Kim, J. Cha, J. J. K. Park, D. Jeon, and Y. Park, “Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing,” IEEE Computer Architecture Letters (CAL), 2019.
  • T. Jang, S. Jeong, D. Jeon, K. D. Choo, D. Sylvester, and D. Blaauw, “A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector,” IEEE Journal of Solid-State Circuits (JSSC), 2018, invited.
  • D. Jeon, Q. Dong, Y. Kim, X. Wang, S. Chen, H. Yu, D. Blaauw, and D. Sylvester, “A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), 2017.
  • Y.-P. Chen, D. Jeon, Y. Lee, Y. Kim, Z. Foo, I. Lee, N. B. Langhals, G. Kruger, H. Oral, O. Berenfeld, Z. Zhang, D. Blaauw, and D. Sylvester, “An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring,” IEEE Journal of Solid-State Circuits (JSSC), 2015, invited.
  • D. Jeon, M. B. Henry, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, and D. Sylvester, “An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), 2014.
  • D. Jeon, M. Seok, Z. Zhang, D. Blaauw, and D. Sylvester, “A Design Methodology for Voltage Overscaled Ultra-Low Power Systems,” IEEE Transactions on Circuits and Systems II (TCAS-II), 2013.
  • D. Jeon, M. Seok, C. Chakrabarti, D. Blaauw, and D. Sylvester, “A Super-Pipelined Energy Efficient Subthreshold 240MS/s FFT Core in 65nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), 2012, invited.