{"id":17,"date":"2016-07-09T07:01:02","date_gmt":"2016-07-09T07:01:02","guid":{"rendered":"http:\/\/147.47.120.188\/?page_id=17"},"modified":"2026-04-01T13:16:21","modified_gmt":"2026-04-01T13:16:21","slug":"publications","status":"publish","type":"page","link":"https:\/\/mms.snu.ac.kr\/?page_id=17","title":{"rendered":"Publications"},"content":{"rendered":"<h3>Conference Proceedings<\/h3>\n<ul>\n<li>M. Kang, D. Lee, S. Jeong, K. Shin, and D. Jeon, &#8220;A 28nm 2GS\/s Remote-Sensing On-Chip Oscilloscope Using Charge-Redistributing Voltage Transfer and Time-Domain Stochastic ADC with 1.6mV Resolution,&#8221;\u00a0<em>IEEE Symposium on VLSI Circuits (<strong>VLSIC<\/strong>)<\/em>, <em>accepted<\/em>.<\/li>\n<li>S. Jeon, S. Park, B. Kim, J. Oh, and D. Jeon, \u201cA 28nm 34mW Zero Knowledge Proof Processor with Reconfigurable Modular Multiplier Array and Memory-based Successive Excess Reduction,\u201d <em>IEEE Custom Integrated Circuits Conference (<strong>CICC<\/strong>)<\/em>, <em>accepted<\/em>.<\/li>\n<li>D. Lee, D. Kim, and D. Jeon, \u201cA Dynamic-Active Static-Sleep 18T Flip-Flop Supporting Retentive Clock Gating in 28nm CMOS,\u201d <em>IEEE Custom Integrated Circuits Conference (<strong>CICC<\/strong>)<\/em>, <em>accepted<\/em>.<\/li>\n<li>S. Jeong*, J. Park*, and D. Jeon, \u201cROM-LTE: A 28nm 16.1TOPS\/W ROM-Based LUT Tensor Engine with Complementary ROM and Switching-Suppressed Latch-Based PE for Fine-Tuning-Free ML Inference,\u201d <em>IEEE Custom Integrated Circuits Conference (<strong>CICC<\/strong>)<\/em>, <em>accepted<\/em>. (*equal contribution)<\/li>\n<li>I. Jeong*, S. Woo*, S. Namkung, and D. Jeon, \u201cHiFC: High-efficiency Flash-based KV Cache Swapping for Scaling LLM Inference,\u201d <em>Conference on Neural Information Processing Systems (<strong>NeurIPS<\/strong>)<\/em>, 2025. (*equal contribution)<\/li>\n<li>B. Yoo, S. Park, S. Lee, and D. Jeon, \u201cAn Energy-Efficient Super-Resolution Processor with Enhanced Tiling Artifact Reduction,\u201d <em>IEEE Asia Pacific Conference on Circuits and Systems (<strong>APCCAS<\/strong>)<\/em>, 2025.<\/li>\n<li>S. Woo, S. Namkung, S. Lee, I. Jeong, B. Kim, and D. Jeon, \u201cPaCA: Partial Connection Adaptation for Efficient Fine-Tuning,\u201d <em>International Conference on Learning Representations (<strong>ICLR<\/strong>)<\/em>, 2025.<\/li>\n<li>J. Oh, J.-X. Liu, Y.-C. Teng, H.-C. Wang, and D. Jeon, &#8220;A 28-nm Real-Time Reinforcement Learning Processor for Mapless Autonomous Navigation with Unified Actor-Critic Network and Inference-on-Request Scheduling,&#8221; <em>IEEE Custom Integrated Circuits Conference (<strong>CICC<\/strong>)<\/em>, 2025.<\/li>\n<li>S. Jeong*, H. Yun*, D. Lee, S. Lee, M. Kang, and D. Jeon, &#8220;An 83.16-TOPS\/W Voltage-Scalable Time-Domain CNN Accelerator with Full-Swing Delay Cell and Gray-Code TDC in 28-nm CMOS,&#8221; <em>IEEE Custom Integrated Circuits Conference (<strong>CICC<\/strong>)<\/em>, 2025. (*equal contribution)<\/li>\n<li>S. Jeong, S. Park, M. Seok, and D. Jeon, &#8220;A 28nm 18.1\u03bcJ\/acquisition End-to-End GPS Acquisition Accelerator with Energy-Accuracy-Driven Mixed-Radix IFFT and ROM-Assisted Computing,&#8221; <em>IEEE International Solid-State Circuits Conference (<strong>ISSCC<\/strong>)<\/em>, 2025.<\/li>\n<li>S. Jang*, S. Jeon*, K. Shin, D. Lee, H. Chi, W. Shin, C. Pyo, J. Kim, and D. Jeon, \u201cWITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory,\u201d <em> IEEE\/ACM Asia and South Pacific Design Automation Conference (<strong>ASP-DAC<\/strong>)<\/em>, 2025. (*equal contribution)<\/li>\n<li>S. Jang, S. Park, and D. Jeon, \u201cEfficient Key Switching Accelerator for Fully Homomorphic Encryption,\u201d <em> IEEE\/ACM Asia and South Pacific Design Automation Conference (<strong>ASP-DAC<\/strong>)<\/em>, 2025.<\/li>\n<li>S. Woo, B. Park, B. Kim, M. Jo, S. J. Kwon, D. Jeon, and D. Lee, \u201cDropBP: Accelerating Fine-Tuning of Large Language Models by Dropping Backward Propagation,\u201d <em>Conference on Neural Information Processing Systems (<strong>NeurIPS<\/strong>)<\/em>, 2024.<\/li>\n<li>D. Lee, S. Kim, M. Kang, S. Jang, S. Park, J. Kim, and D. Jeon, \u201cA 1.22fJ\/cycle 17T Pseudo-Static True Single-Phase Clock Flip-Flop in 14nm FinFET CMOS,\u201d <em>IEEE European Solid-State Electronics Research Conference (<strong>ESSERC<\/strong>)<\/em>, 2024.<\/li>\n<li>S. Park*, K. Shin*, D. Lee, M. Kang, S. Lee, Y. Park, M. Seok, and D. Jeon, &#8220;A 5.6\u03bcW 10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy,&#8221;\u00a0<em>IEEE Symposium on VLSI Circuits (<strong>VLSIC<\/strong>)<\/em>, 2024. (*equal contribution)<\/li>\n<li>S. Woo, S. Lee, and D. Jeon, \u201cALAM: Averaged Low-Precision Activation for Memory-Efficient Training of Transformer Models,\u201d <em>International Conference on Learning Representations (<strong>ICLR<\/strong>)<\/em>, 2024.<\/li>\n<li>M. Kang, S. Kim, Y. Park, S. Jeong, and D. Jeon, \u201cA 28nm All-Digital Droop Detection and Mitigation Circuit Using A Shared Dual-Mode Delay Line with 14.8% V<sub>min<\/sub> Reduction and 42.9% Throughput Gain,\u201d <em>IEEE Custom Integrated Circuits Conference (<strong>CICC<\/strong>)<\/em>, 2024.<\/li>\n<li>S. Jeong, J. Oh, and D. Jeon, \u201cA 28nm 157TOPS\/W 446.9Kb\/mm<sup>2<\/sup> Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference,\u201d <em>IEEE Custom Integrated Circuits Conference (<strong>CICC<\/strong>)<\/em>, 2024.<\/li>\n<li>S. Lee, J. Park, and D. Jeon, \u201cA 4.27TFLOPS\/W FP4\/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array,\u201d <em>IEEE European Solid-State Circuits Conference (<strong>ESSCIRC<\/strong>)<\/em>, 2023.<\/li>\n<li>S. Woo and D. Jeon, \u201cLearning with Auxiliary Activation for Memory-Efficient Training,\u201d <em>International Conference on Learning Representations (<strong>ICLR<\/strong>)<\/em>, 2023.<\/li>\n<li>S. Park, S. Lee, J. Park, H.-S. Choi, and D. Jeon, &#8220;A 0.81mm<sup>2<\/sup> 740\u00b5W Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS,&#8221; <em>IEEE International Solid-State Circuits Conference (<strong>ISSCC<\/strong>)<\/em>, 2023.<\/li>\n<li>S. Jeong, J. Park, and D. Jeon, \u201cA 28nm 1.644TFLOPS\/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training,\u201d <em>IEEE European Solid-State Circuits Conference (<strong>ESSCIRC<\/strong>)<\/em>, 2022.<\/li>\n<li>S. Lee, J. Park, and D. Jeon, \u201cToward Efficient Low-Precision Training: Data Format Optimization and Hysteresis Quantization,\u201d <em>International Conference on Learning Representations (<strong>ICLR<\/strong>)<\/em>, 2022.<\/li>\n<li>S. Woo, J. Park, J. Hong, and D. Jeon, \u201cActivation Sharing with Asymmetric Paths Solves Weight Transport Problem without Bidirectional Connection,\u201d <em>Conference on Neural Information Processing Systems (<strong>NeurIPS<\/strong>)<\/em>, 2021.<\/li>\n<li>J. Park*, S. Lee*, and D. Jeon, \u201cA 40nm 4.81TFLOPS\/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree,\u201d <em>IEEE International Solid-State Circuits Conference (<strong>ISSCC<\/strong>)<\/em>, 2021. (*equal contribution)<\/li>\n<li>S. Park and D. Jeon, &#8220;A Modified Serial Commutator Architecture for Real-Valued Fast Fourier Transform,&#8221;\u00a0<em>IEEE International Workshop on Signal Processing Systems (<strong>SiPS<\/strong>)<\/em>, 2020.<\/li>\n<li>J. Park, J. Lee, and D. Jeon, \u201cA 65nm 236.5nJ\/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback,\u201d <em>IEEE International Solid-State Circuits Conference (<strong>ISSCC<\/strong>)<\/em>, 2019.<\/li>\n<li>T. Jang, S. Jeong, D. Jeon, K. D. Choo, D. Sylvester, and D. Blaauw, &#8220;A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment,&#8221; <em>IEEE International Solid-State Circuits Conference (<strong>ISSCC<\/strong>)<\/em>, 2017.<\/li>\n<li>S. M. A. Zeinolabedin,\u00a0A. T. Do, D. Jeon, D. Sylvester, and T. T.-H. Kim, &#8220;A 128-channel spike sorting processor featuring 0.175 \u00b5W and 0.0033 mm<sup>2<\/sup> per channel in 65-nm CMOS,&#8221;\u00a0<em>IEEE Symposium on VLSI Circuits (<strong>VLSIC<\/strong>)<\/em>, 2016.<\/li>\n<li>D. Jeon,\u00a0N. Ickes, P. Raina, H.-C. Wang, and A. P. Chandrakasan, &#8220;A 0.6V, 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired,&#8221; <em>IEEE International Solid-State Circuits Conference (<strong>ISSCC<\/strong>)<\/em>, 2016.<\/li>\n<li>D. Jeon, Q. Dong, Y. Kim, X. Wang, S. Chen, H. Yu, D. Blaauw, and D. Sylvester, \u201cA 23mW Face Recognition Accelerator in 40nm CMOS with Mostly-Read 5T Memory,\u201d <em>IEEE Symposium on VLSI Circuits (<strong>VLSIC<\/strong>)<\/em>, 2015.<\/li>\n<li>S. Jeong, W. Jung, D. Jeon, O. Berenfeld, H. Oral, G. Kruger, D. Blaauw, and D. Sylvester, &#8220;A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications,&#8221;\u00a0<em>IEEE Symposium on VLSI Circuits (<strong>VLSIC<\/strong>)<\/em>, 2015.<\/li>\n<li>I. Lee, Y. Kim, S. Bang, G. Kim, H. Ha, Y.-P. Chen, D. Jeon, S. Jeong, W. Jung, M. H. Ghaed, Z. Foo, Y. Lee, J.-Y. Sim, D. Sylvester, and D. Blaauw, &#8220;Circuit techniques for miniaturized biomedical sensors,&#8221; <em>IEEE Custom Integrated Circuits Conference (<strong>CICC<\/strong>)<\/em>, 2014.<\/li>\n<li>D. Jeon, Y.-P. Chen, Y. Lee, Y. Kim, Z. Foo, G. Kruger, H. Oral, O. Berenfeld, Z. Zhang, D.\u00a0Blaauw, and D. Sylvester, \u201cAn Implantable 64nW ECG Monitoring Mixed-Signal SoC for Arrhythmia Diagnosis,\u201d <em>IEEE International Solid-State Circuits Conference (<strong>ISSCC<\/strong>)<\/em>, 2014.<\/li>\n<li>D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw and D. Sylvester, \u201cA low-power VGA full-frame feature extraction processor ,\u201d<em> IEEE International Conference on Acoustics, Speech and Signal Processing (<strong>ICASSP<\/strong>)<\/em>, 2013.<\/li>\n<li>D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw and D. Sylvester, \u201cA 470mV 2.7mW Feature Extraction-Accelerator for Micro-Autonomous Vehicle Navigation in 28nm CMOS,\u201d <em>IEEE International Solid-State Circuits Conference (<strong>ISSCC<\/strong>)<\/em>, 2013.<\/li>\n<li>M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester, \u201cExtending Energy-Saving Voltage Scaling in Ultra Low Voltage Integrated Circuit Designs,\u201d <em>International Conference on IC Design and Technology (<strong>ICICDT<\/strong>)<\/em>, 2012. (<em>invited<\/em>)<\/li>\n<li>M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester, \u201cPipeline Strategy for Improving Optimal Energy Efficiency in Ultra-Low Voltage Design,\u201d <em>ACM\/IEEE Design Automation <\/em><em>Conference (<strong>DAC<\/strong>)<\/em>, 2011.<\/li>\n<li>D. Jeon, M. Seok, C. Chakrabarti, D. Blaauw and D. Sylvester, \u201cEnergy-optimized high performance FFT processor,\u201d <em>IEEE International Conference on Acoustics, Speech and Signal Processing (<strong>ICASSP<\/strong>)<\/em>, 2011.<\/li>\n<li>M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester, \u201cA 0.27V, 30MHz, 17.7nJ\/transform 1024-pt complex FFT core with ultrapipelining,\u201d <em>IEEE International Solid-State Circuits Conference (<strong>ISSCC<\/strong>)<\/em>, 2011.<\/li>\n<\/ul>\n<h3>Journal Publications<\/h3>\n<ul>\n<li>C. Seong, S. Lee, B. Kim, and D. Jeon, &#8220;An Area- and Energy-Efficient Point-Based 3D Object Detection Processor with Feature-Decoupled PointNet for Autonomous Driving,&#8221; <em>IEEE Transactions on Circuits and Systems I (<strong>TCAS-I<\/strong>)<\/em>, <em>accepted<\/em>.<\/li>\n<li>S. Jeon*, S. Jang*, K. Shin, D. Lee, H. Chi, W. Shin, C. Pyo, and D. Jeon, &#8220;Weighted Coding Scheme for Noise Reduction in Silicon Interposer of HBM,&#8221; <em>IEEE Transactions on VLSI Systems (<strong>TVLSI<\/strong>)<\/em>, 2026. (*equal contribution)<\/li>\n<li>J. Oh, J.-X. Liu, Y.-C. Teng, H.-C. Wang, and D. Jeon, &#8220;A Real-Time Deep Reinforcement Learning Processor for Mapless Autonomous Navigation With Unified Actor-Critic Network and Inference-on-Request Scheduling,&#8221; <em>IEEE Journal of Solid-State Circuits (<strong>JSSC<\/strong>)<\/em>, 2026. (<em>invited<\/em>)<\/li>\n<li>D. Lee, H. Chae, J. Kim, and D. Jeon, &#8220;Design Approaches for Efficient Parallel Pseudo-Random Ternary Sequence Generation,&#8221; <em>IEEE Transactions on Circuits and Systems I (<strong>TCAS-I<\/strong>)<\/em>, 2026.<\/li>\n<li>B. Kim, S. Lee, B. Yoo, and D. Jeon, &#8220;An Energy-Efficient 3D Semantic Segmentation Processor With Offset-Wise Weight Quantization,&#8221; <em>IEEE Transactions on Circuits and Systems II (<strong>TCAS-II<\/strong>)<\/em>, 2025.<\/li>\n<li>S. Lee, B. Kim, J. Park, and D. Jeon, &#8220;CLAT: A Clustering-Based Attention Transformer Accelerator for Low-Latency Text Generation in LLMs,&#8221; <em>IEEE Transactions on Circuits and Systems I (<strong>TCAS-I<\/strong>)<\/em>, 2025.<\/li>\n<li>S. Park, S. Lee, J. Park, H.-S. Choi, K. Lee, and D. Jeon, &#8220;A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS,&#8221; <em>IEEE Journal of Solid-State Circuits (<strong>JSSC<\/strong>)<\/em>, 2025.<\/li>\n<li>W. Lee, K. Kim, W. Ahn, J. Kim, and D. Jeon, &#8220;A Real-Time Object Detection Processor with XNOR-based Variable-Precision Computing Unit,&#8221; <em>IEEE Transactions on VLSI Systems (<strong>TVLSI<\/strong>)<\/em>, 2023.<\/li>\n<li>Y. Ko, S. Kim, K. Shin, Y. Park, S. Kim, and D. Jeon, &#8220;A 65nm 12.92nJ\/inference Mixed-Signal Neuromorphic Processor for Image Classification,&#8221; <em>IEEE Transactions on Circuits and Systems II (<strong>TCAS-II<\/strong>)<\/em>, 2023.<\/li>\n<li>Y. Park and D. Jeon, &#8220;A 270mA Self-Calibrating-Clocked Output-Capacitor-Free LDO with 0.15-1.15V Output Range and 0.183fs FoM,&#8221; <em>IEEE Transactions on VLSI Systems (<strong>TVLSI<\/strong>)<\/em>, 2022.<\/li>\n<li>J. Hong, S. Kim, and D. Jeon, &#8220;An Automatic Circuit Design Framework for Level Shifter Circuits,&#8221; <em>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (<strong>TCAD<\/strong>)<\/em>, 2022.<\/li>\n<li>S. Kim, W. Lee, S. Kim, S. Park, and D. Jeon, &#8220;An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network,&#8221; <em>IEEE Transactions on Circuits and Systems II (<strong>TCAS-II<\/strong>)<\/em>, 2022.<\/li>\n<li>J. Park, S. Lee, and D. Jeon, &#8220;A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees,&#8221; <em>IEEE Journal of Solid-State Circuits (<strong>JSSC<\/strong>)<\/em>, 2022.<\/li>\n<li>C. Seong, W. Lee, and D. Jeon, &#8220;A Multi-Channel Spike Sorting Processor with Accurate Clustering Algorithm Using Convolutional Autoencoder,&#8221; <em>IEEE Transactions on Biomedical Circuits and Systems (<strong>TBioCAS<\/strong>)<\/em>, 2021.<\/li>\n<li>G. Lee, S. Lee, and D. Jeon, &#8220;Dynamic Block-Wise Local Learning Algorithm for Efficient Neural Network Training,&#8221;\u00a0<em>IEEE Transactions on VLSI Systems (<strong>TVLSI<\/strong>)<\/em>, 2021.<\/li>\n<li>K. Shin, D.-W. Jee, and D. Jeon, &#8220;A 65nm 0.6-1.2V Low-Dropout Regulator Using Voltage-Difference-to-Time Converter with Direct Output Feedback,&#8221;\u00a0<em>IEEE Transactions on Circuits and Systems II (<strong>TCAS-II<\/strong>)<\/em>, 2021.<\/li>\n<li>J. Park, J. Lee, and D. Jeon, &#8220;A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback,&#8221; <em>IEEE Journal of Solid-State Circuits (<strong>JSSC<\/strong>)<\/em>, 2020. (<em>invited<\/em>)<\/li>\n<li>S. Kim, J. Lee, I. Kwon, and D. Jeon, &#8220;<span id=\"articleTitle\" class=\"els-display-text\">TID-Tolerant Inverter Designs for Radiation-Hardened Digital Systems<\/span>,&#8221; <em>Nuclear Instruments and Methods in Physics Research Section A (<strong>NIMA<\/strong>)<\/em>, <em>2020<\/em>.<\/li>\n<li>S. Moon, K. Shin, and D. Jeon, &#8220;Enhancing Reliability of Analog Neural Network Processors,&#8221; <em>IEEE Transactions on VLSI Systems (<strong>TVLSI<\/strong>)<\/em>, 2019.<\/li>\n<li>J. Park, Y. Kwon, Y. Park, and D. Jeon, &#8220;Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors,&#8221; <em>IEEE Access<\/em>, 2019.<\/li>\n<li>J. Kim, J. Cha, J. J. K. Park, D. Jeon, and Y. Park, &#8220;Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing,&#8221; <em>IEEE Computer Architecture Letters (<strong>CAL<\/strong>)<\/em>, 2019.<\/li>\n<li>J. Lee, D.-W. Jee, and D. Jeon, &#8220;Power-up control techniques for reliable SRAM PUF,&#8221; <em>IEICE Electronics Express (<strong>Elex<\/strong>)<\/em>, 2019.<\/li>\n<li>T. Jang, S. Jeong, D. Jeon, K. D. Choo, D. Sylvester, and D. Blaauw, &#8220;A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector,&#8221; <em>IEEE Journal of Solid-State Circuits (<strong>JSSC<\/strong>)<\/em>, 2018. (<em>invited<\/em>)<\/li>\n<li>D. Jeon, Q. Dong, Y. Kim, X. Wang, S. Chen, H. Yu, D. Blaauw, and D. Sylvester, &#8220;A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS,&#8221;\u00a0<em>IEEE Journal of Solid-State Circuits (<strong>JSSC<\/strong>)<\/em>, 2017.<\/li>\n<li>Y.-P. Chen, D. Jeon, Y. Lee, Y. Kim, Z. Foo, I. Lee, N. B. Langhals, G. Kruger, H. Oral, O. Berenfeld, Z. Zhang, D. Blaauw, and D. Sylvester, \u201cAn Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring,\u201d <em>IEEE Journal of Solid-State Circuits (<strong>JSSC<\/strong>)<\/em>, 2015. (<em>invited<\/em>)<\/li>\n<li>D. Jeon, M. B. Henry, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, and D. Sylvester, \u201cAn Energy Efficient\u00a0Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS,\u201d <em>IEEE Journal of Solid-State Circuits (<strong>JSSC<\/strong>)<\/em>, 2014.<\/li>\n<li>D. Jeon, M. Seok, Z. Zhang, D. Blaauw, and D. Sylvester, \u201cA Design Methodology for Voltage Overscaled Ultra-Low Power Systems,\u201d <em>IEEE Transactions on Circuits and Systems II (<strong>TCAS-II<\/strong>)<\/em>, 2013.<\/li>\n<li>D. Jeon, M. Seok, C. Chakrabarti, D. Blaauw, and D. Sylvester, \u201cA Super-Pipelined Energy Efficient Subthreshold 240MS\/s FFT Core in 65nm CMOS,\u201d <em>IEEE Journal of Solid-State Circuits (<\/em><em><strong>JSSC<\/strong>)<\/em>, 2012. (<em>invited<\/em>)<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Conference Proceedings M. Kang, D. Lee, S. Jeong, K. Shin, and D. Jeon, &#8220;A 28nm 2GS\/s Remote-Sensing On-Chip Oscilloscope Using Charge-Redistributing Voltage Transfer and Time-Domain Stochastic ADC with 1.6mV Resolution,&#8221;\u00a0IEEE Symposium on VLSI Circuits (VLSIC), accepted. S. Jeon, S. Park, B. Kim, J. Oh, and D. Jeon, \u201cA 28nm 34mW Zero Knowledge Proof Processor with [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-17","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/pages\/17","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=17"}],"version-history":[{"count":54,"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/pages\/17\/revisions"}],"predecessor-version":[{"id":466,"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/pages\/17\/revisions\/466"}],"wp:attachment":[{"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=17"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}