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<\/a><\/p>\nDue to the recent shift in the machine learning community towards using non-sparse activation functions such as Leaky ReLU or Swish for better training convergence, state-of-the-art models no longer exhibit the sparsity found in conventional ReLU-based models. Moreover, more difficult tasks such as image super-resolution require higher precision than plain 8-bit integers not just for training, but for inference without large accuracy degradation.\u00a0To overcome such challenges,\u00a0we developed a deep learning processor with support for efficient inference and training for various modern neural networks. Our key contributions are: (1) an 8-bit floating point data format with shared exponent bias (FP8-SEB) for robust training in low precision, (2) a processing architecture employing 24-way Fused Multiply-Add (FMA) trees and high-precision accumulators that improves training accuracy and energy efficiency, and (3) 2-D routing scheme on input\/output points of processing element array for flexible training of various models with minimal hardware overhead. Based on these contributions, our neural network training processor achieves 4.81TFLOPS\/W energy efficiency, 567GFLOPS performance, and robust training on various models including Generative Adversarial Network (GAN), Long-Short-Term-Memory (LSTM), transformer models, as well as Convolutional Neural Network (CNN).<\/p>\n
Publications: ISSCC 2021<\/a>, JSSC 2022<\/a> Neuromorphic computing algorithms such as SNN (Spiking Neural Network) offer great energy efficiency, but they are not considered\u00a0practical solutions yet due to low algorithm accuracy. In this work, we proposed a new neuromorphic computing algorithm based on\u00a0bio-plausible approach, which provides similar performance to SGD-based learning scheme.\u00a0By combining\u00a0a well-optimized architecture to further improve computation efficiency,\u00a0we designed a ultra-low power\u00a0on-chip trainable neuromorphic processor for classification tasks. Training energy of 254.3 nJ\/image is achieved through a hardware-oriented direct feedback algorithm, out-of-order weight updates, and an update-skipping mechanism. During prediction, the processor achieves 97.83% MNIST recognition accuracy with 236.5 nJ\/prediction. This result demonstrates a 7.5% training energy overhead, while providing superior energy efficiency than recent inference-only designs.<\/p>\n Publications: ISSCC 2019<\/a>, JSSC 2020<\/a> Large-scale digital SoCs must be accompanied by a reliable, efficient power management system. Low-dropout regulator (LDO) is one of the key blocks in those systems, where\u00a0it must generate a constant output voltage\u00a0under a wide range of input voltage and load current. We\u00a0proposed a new LDO topology\u00a0using a voltage-difference-to-time converter and direct output feedback path, and the design combines the advantages of conventional digital and analog LDOs.\u00a0 The\u00a0fabricated LDO achieves\u00a00.202fs FOM, which is significantly lower than prior works.<\/p>\n Publication:\u00a0TCAS-II 2021<\/a><\/p>\n Under radiation emitting circumstances, high energy particles induce accumulation of holes in the oxide. The accumulated holes modify transistor characteristics such as threshold voltage,\u00a0degrading hardware reliability.\u00a0In order to\u00a0avoid transistor malfunction\u00a0in a circuit, radiation hardening by design (RHBD) techniques\u00a0have been\u00a0actively studied. In this project, we applied several topologies to\u00a0an inverter which is\u00a0a\u00a0basic building block of all digital systems, and\u00a0experimentally analyze the\u00a0reliability of each\u00a0circuit topology under high radiation dose. Measured results confirm that the stacked NMOS topology performs best, reducing switching point variation by >10x and average power by 20%\u00a0at the expense of\u00a030% area overhead.<\/p>\n Publication:\u00a0NIMA 2020<\/a><\/p>\n Please note that the completed projects shown below were conducted at the University of Michigan (Advisor: Prof. Dennis Sylvester) and MIT (Advisor: Prof. Anantha Chandrakasan).<\/em><\/p>\n In this project, we developed a fully-integrated navigation system for the visually impaired. Since processing 3-D imaging data using exsiting algorithms is computationally expensive, commercial off-the-shelf processors are not able to process 3-D data in real time. To tackle this issue, we designed a highly energy-efficient vision processor tailored for general 3-D image data processing algorithms. By designing a new hardware architecture as well as optimizing conventional algorithms further, the processor fabricated in 40nm CMOS technology consumes only 8mW while processing 30fps 3-D input video stream in real time. We also implemented a fully-integrated navigation system and confirmed its functionality in various experiments.<\/p>\n Publication: ISSCC 2016<\/span><\/a> \u00a0 Face detection and recognition\u00a0are now available on many mobile platforms. For instance, facebook app can reliably detect faces from uploaded photos. However, we wanted to take one step further and design a complete standalone\u00a0face recognition system that has both face detection and recognition features and processes input\u00a0video in real time. Based on classical but very reliable algorithms including cascade classifiers and Support Vector Machine (SVM), we optimized hardware architecture to minimize processing overheads. In addition, we proposed a new SRAM design tailored for this specific application to tackle the issue of large leakage current in advaned CMOS processes. The\u00a0fabricated design\u00a0consumes 23mW while processing HD video with 5.5fps throughput.<\/p>\n Publication: Symposium on VLSI Circuits 2015<\/span><\/a><\/p>\n With continuous semiconductor technology scaling, recently small form factor implantable biomedical systems gained lots of attentions due to its\u00a0enhanced computation capacity. In this project, we implemented\u00a0a syringe-implantable ECG monitoring system primarily for arrhythmia detection. The system has a powerful ARM Cortex-M0 paired with custom digital signal processing blocks, which delivers both\u00a0enough computing power and flexibility. The proposed system only consumes 65nW while monitoring ECG waveforms continuously and we confirmed its functionality in the experiment using a live sheep heart.<\/p>\n Publications: ISSCC 2014<\/span><\/a>, JSSC 2015<\/span><\/a><\/p>\n Visual feature extraction is a\u00a0method to extract useful information from input image or video, and this information can be later used in other algorithms including object recognition and pose estimation. Since it is a key part in computer vision\u00a0and generally requires a large amount of computation, we designed a specialized\u00a0accelerator to significantly reduce processing overhead. Starting from original Speeded-Up Robust Features (SURF)\u00a0algorithm we modified it from hardware design perspective, which resulted in more hardware-friendly algorithm. We also proposed a low-power robust FIFO design to mitigate tremendous amount of leakage power in low operating voltages. The proposed design provides 3.5x efficiency improvements than state-of-the-art designs.<\/p>\n Publications: ISSCC 2013<\/span><\/a>, JSSC 2014<\/span><\/a> \u00a0 Fast Fourier Transform (FFT) is one of the most famous digital signal processing algorithms used in many platforms. In this project, we targeted achieving maximum energy efficiency for the given algorithm in order to increase the lifetime of\u00a0battery-powered systems. We first developed a low leakage, energy-efficient parallel FFT architecture. This architecture was applied to the final FFT processor along with a novel circuit technique called “super-pipelining”, resulting in 2x better energy efficiency than previous works.<\/p>\n Publications: ISSCC 2011<\/span><\/a>, JSSC 2012<\/span><\/a><\/p>\n","protected":false},"excerpt":{"rendered":" Current research projects Energy-efficient\u00a0machine learning processors We are designing highly energy-efficient machine learning processors by developing both hardware-friendly algorithms and low-power hardware design techniques. Our ultimate goal is to build practical machine-learning processors that exhibit both state-of-the-art algorithm performance and energy efficiency by finding the best algorithm-hardware combination. For instance, we developed a neuromorphic processor […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-12","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/pages\/12","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=12"}],"version-history":[{"count":46,"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/pages\/12\/revisions"}],"predecessor-version":[{"id":471,"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=\/wp\/v2\/pages\/12\/revisions\/471"}],"wp:attachment":[{"href":"https:\/\/mms.snu.ac.kr\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=12"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\nAwards:
\n– Gold Award (1st place in circuit design), Samsung Humantech, 2021.
\n– Best Design Award, ACM\/IEEE International Symposium on Low Power Electronics and Design, 2021.<\/p>\n<\/h3>\n
Energy-efficient neuromorphic processor with on-chip training<\/h3>\n
<\/a> <\/a> <\/a><\/p>\n
\nMedia coverage: Dong-A Ilbo (Korean Newspaper)<\/a><\/p>\n<\/h3>\n
Low-dropout regulator\u00a0with high efficiency and wide operating range<\/h3>\n
<\/a><\/a><\/a><\/p>\n<\/h3>\n
Radiation hardening by design<\/h3>\n
<\/a>\u00a0<\/a>\u00a0<\/a><\/p>\nNavigation system for the\u00a0visually impaired<\/h3>\n
<\/a><\/a><\/a><\/p>\n<\/a><\/a><\/p>\n
\nSelected media coverage: EE Times,<\/span><\/a> Tech Times<\/span><\/a>, Qmed<\/span><\/a>, The Daily Dot<\/span><\/a><\/p>\nFace recognition system for mobile platforms<\/h3>\n
<\/a><\/a><\/p>\nSyringe-implantable ECG monitoring device<\/h3>\n
<\/a><\/a><\/a><\/p>\n<\/h3>\n
Feature extraction accelerator<\/h3>\n
<\/a><\/a><\/p>\n
\nMedia coverage: IEEE Spectrum<\/span><\/a><\/p>\nEnergy-efficient FFT processor<\/h3>\n
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